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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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13. Configuring Cyclone II  
Devices  
CII51013-3.1  
Cyclone® II devices use SRAM cells to store configuration data. Since  
SRAM memory is volatile, configuration data must be downloaded to  
Cyclone II devices each time the device powers up. You can use the active  
serial (AS) configuration scheme, which can operate at a DCLKfrequency  
up to 40 MHz, to configure Cyclone II devices. You can also use the  
passive serial (PS) and Joint Test Action Group (JTAG)-based  
configuration schemes to configure Cyclone II devices. Additionally,  
Cyclone II devices can receive a compressed configuration bitstream and  
decompress this data on-the-fly, reducing storage requirements and  
configuration time.  
Introduction  
This chapter explains the Cyclone II configuration features and describes  
how to configure Cyclone II devices using the supported configuration  
schemes. This chapter also includes configuration pin descriptions and  
the Cyclone II configuration file format.  
f
For more information on setting device configuration options or creating  
configuration files, see the Software Settings chapter in the Configuration  
Handbook.  
You can use the AS, PS, and JTAG configuration schemes to configure  
Cyclone II devices. You can select which configuration scheme to use by  
driving the Cyclone II device MSELpins either high or low as shown in  
Table 13–1. The MSELpins are powered by the VCCIO power supply of the  
bank they reside in. The MSEL[1..0]pins have 9-kΩinternal pull-down  
resistors that are always active. During power-on reset (POR) and  
reconfiguration, the MSELpins have to be at LVTTL VIL or VIH levels to be  
considered a logic low or logic high, respectively. Therefore, to avoid any  
problems with detecting an incorrect configuration scheme, you should  
connect the MSEL[]pins to the VCCIO of the I/O bank they reside in and  
GND without any pull-up or pull-down resistors. The MSEL[]pins  
should not be driven by a microprocessor or another device.  
Cyclone II  
Configuration  
Overview  
Altera Corporation  
February 2007  
13–1  
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