Contents
Phase Lock Loop (PLL) .................................................................................................................. 9–15
Clock Delay Control ....................................................................................................................... 9–15
DQS Postamble ............................................................................................................................... 9–16
DDR Input Registers ...................................................................................................................... 9–18
DDR Output Registers ................................................................................................................... 9–21
Bidirectional DDR Registers ......................................................................................................... 9–22
Conclusion ............................................................................................................................................ 9–24
Document Revision History ............................................................................................................... 9–25
Section IV. I/O Standards
Revision History .................................................................................................................................... 9–1
Chapter 10. Selectable I/O Standards in Cyclone II Devices
Introduction .......................................................................................................................................... 10–1
Supported I/O Standards ................................................................................................................... 10–1
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) .......................................................................... 10–3
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) ..................................................................... 10–4
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus Specification Revision 3.0) ............. 10–4
3.3-V PCI-X ...................................................................................................................................... 10–6
Easy-to-Use, Low-Cost PCI Express Solution ............................................................................ 10–6
2.5-V LVTTL (EIA/JEDEC Standard EIA/JESD8-5) ................................................................. 10–7
2.5-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-5) ............................................................ 10–7
SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A) ......................................................... 10–7
Pseudo-Differential SSTL-2 ........................................................................................................... 10–8
1.8-V LVTTL (EIA/JEDEC Standard EIA/JESD8-7) ................................................................. 10–9
1.8-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-7) .......................................................... 10–10
SSTL-18 Class I and II .................................................................................................................. 10–10
1.8-V HSTL Class I and II ............................................................................................................ 10–11
Pseudo-Differential SSTL-18 Class I and Differential SSTL-18 Class II ............................... 10–12
1.8-V Pseudo-Differential HSTL Class I and II ........................................................................ 10–13
1.5-V LVCMOS (EIA/JEDEC Standard JESD8-11) .................................................................. 10–14
1.5-V HSTL Class I and II ............................................................................................................ 10–14
1.5-V Pseudo-Differential HSTL Class I and II ........................................................................ 10–15
LVDS, RSDS and mini-LVDS ..................................................................................................... 10–16
Differential LVPECL .................................................................................................................... 10–17
Cyclone II I/O Banks ........................................................................................................................ 10–18
Programmable Current Drive Strength .......................................................................................... 10–24
Voltage-Referenced I/O Standard Termination ...................................................................... 10–26
Differential I/O Standard Termination .................................................................................... 10–26
I/O Driver Impedance Matching (RS) and Series Termination (RS) ..................................... 10–27
Pad Placement and DC Guidelines ................................................................................................. 10–27
Differential Pad Placement Guidelines ..................................................................................... 10–28
VREF Pad Placement Guidelines ................................................................................................. 10–29
DC Guidelines ............................................................................................................................... 10–32
5.0-V Device Compatibility .............................................................................................................. 10–34
Altera Corporation
vii
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
