Cyclone II Architecture
Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration
io_clk[5..0]
Column
or Row
Interconect
OE
OE Register
PRN
D
Q
V
CCIO
clkout
ENA
Optional
PCI Clamp
CLRN
ce_out
V
CCIO
Programmable
Pull-Up
aclr/prn
Resistor
Chip-Wide Reset
Output Register
PRN
Output
Pin Delay
D
Q
ENA
Open-Drain Output
sclr/preset
CLRN
data_in1
data_in0
Bus Hold
Input Pin to
Input Register Delay
or Input Pin to
Logic Array Delay
Input Register
PRN
D
Q
ENA
clkin
CLRN
ce_in
The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.
Altera Corporation
February 2007
2–43
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
