Introduction
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133-MHz PCI-X 1.0 specification compatibility
High-speed external memory support, including DDR, DDR2,
and SDR SDRAM, and QDRII SRAM supported by drop in
Altera IP MegaCore functions for ease of use
Three dedicated registers per I/O element (IOE): one input
register, one output register, and one output-enable register
Programmable bus-hold feature
Programmable output drive strength feature
Programmable delays from the pin to the IOE or logic array
I/O bank grouping for unique VCCIO and/or VREF bank
settings
MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and
3.3-interfaces
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Hot-socketing operation support
Tri-state with weak pull-up on I/O pins before and during
configuration
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Programmable open-drain outputs
Series on-chip termination support
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Flexible clock management circuitry
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Hierarchical clock network for up to 402.5-MHz performance
Up to four PLLs per device provide clock multiplication and
division, phase shifting, programmable duty cycle, and external
clock outputs, allowing system-level clock management and
skew control
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Up to 16 global clock lines in the global clock network that drive
throughout the entire device
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Device configuration
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Fast serial configuration allows configuration times less than
100 ms
Decompression feature allows for smaller programming file
storage and faster configuration times
Supports multiple configuration modes: active serial, passive
serial, and JTAG-based configuration
Supports configuration through low-cost serial configuration
devices
Device configuration supports multiple voltages (either 3.3, 2.5,
or 1.8 V)
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Intellectual property
Altera megafunction and Altera MegaCore function support,
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and Altera Megafunctions Partners Program (AMPPSM
megafunction support, for a wide range of embedded
processors, on-chip and off-chip interfaces, peripheral
)
functions, DSP functions, and communications functions and
Altera Corporation
February 2008
1–3
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
