DC Characteristics and Timing Specifications
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 2 of 2)
–6 Speed
Grade
–7 Speed
Grade (4)
Fast Corner (3)
–8 Speed Grade
Number
of
Settings
Paths
Affected
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
InputDelay Pad ->
from Pin to I/O input
8
2
0
0
2669
2802
0
4482
—
0
0
4834
4671
0
4859
—
ps
ps
—
—
Input
register
Register
Delay from I/O
0
0
308
324
0
572
—
0
0
648
626
0
682
—
ps
ps
Output
output
—
—
Register to register -
Output Pin > Pad
Notes to Table 5–37 :
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
(3) The value in the first row represents the fast corner timing parameter for industrial and automotive devices. The
second row represents the fast corner timing parameter for commercial devices.
(4) The value in the first row is for automotive devices. The second row is for commercial devices.
Default Capacitive Loading of Different I/O Standards
Refer to Table 5–38 for default capacitive loading of different I/O
standards.
Table 5–38. Default Loading of Different I/O Standards for Cyclone II Device
(Part 1 of 2)
I/O Standard
Capacitive Load
Unit
LVTTL
LVCMOS
2.5V
0
0
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
0
1.8V
0
1.5V
0
PCI
10
10
0
PCI-X
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
0
0
Altera Corporation
February 2008
5–31
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
