DC Characteristics and Timing Specifications
EP2C70 Clock Timing Parameters
Tables 5–33 and 5–34 show the clock timing parameters for EP2C70
devices.
Table 5–33. EP2C70 Column Pins Global Clock Timing Parameters
Fast Corner
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Parameter
Unit
Industrial
Commercial
1.651
tCIN
1.575
1.589
2.914
2.948
0.27
3.105
3.137
0.268
0.3
3.174
3.203
0.089
0.118
ns
ns
ns
ns
tCOUT
1.666
tPLLCIN
tPLLCOUT
–0.149
–0.135
–0.158
–0.143
0.304
Table 5–34. EP2C70 Row Pins Global Clock Timing Parameters
Fast Corner
–6 Speed
–7 Speed
Grade
–8 Speed
Grade
Parameter
Unit
Grade
Industrial
1.463
Commercial
1.533
tCIN
2.753
2.769
0.109
0.125
2.927
2.940
0.09
3.010
3.018
ns
ns
ns
ns
tCOUT
1.465
1.535
tPLLCIN
tPLLCOUT
–0.261
–0.259
–0.276
–0.274
–0.075
–0.067
0.103
Clock Network Skew Adders
Table 5–35 shows the clock network specifications.
Table 5–35. Clock Network Specifications
Name
Description
Max
Unit
Clock skew adder
EP2C5/A, EP2C8/A (1)
Inter-clock network, same bank
88
88
ps
ps
Inter-clock network, same side and
entire chip
Clock skew adder
EP2C15A, EP2C20/A,
EP2C35, EP2C50,
EP2C70 (1)
Inter-clock network, same bank
118
138
ps
ps
Inter-clock network, same side and
entire chip
Note to Table 5–35:
(1) This is in addition to intra-clock network skew, which is modeled in the
Quartus II software.
Altera Corporation
February 2008
5–29
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
