Timing Specifications
Table 5–47. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Symbol
Description
Sampling window
SW
The period of time during which the data must be valid in order for you
to capture it correctly. Sampling window is the sum of the setup time,
hold time, and jitter. The window of tSU + tH is expected to be centered
in the sampling window.
SW = TUI – TCCS – (2 × RSKM)
Receiver input skew
margin
RSKM
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2
Input jitter (peak to peak)
Output jitter (peak to peak)
Signal rise time
—
—
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Low-to-high transmission time.
tRISE
tFALL
tLOCK
Signal fall time
High-to-low transmission time.
Lock time
Lock time for high-speed transmitter and receiver PLLs.
Figure 5–3. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Sampling Window (SW)
Internal Clock
TCCS
RSKM
RSKM
TCCS
Receiver
Input Data
Figure 5–4 shows the high-speed I/O timing budget.
5–56
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
