DC Characteristics and Timing Specifications
Table 5–8 shows the recommended operating conditions for user I/O
pins with differential I/O standards.
Table 5–8. Recommended Operating Conditions for User I/O Pins Using Differential Signal I/O Standards
V
CCIO (V)
VID (V) (1)
VICM (V)
Typ
VIL (V)
VIH (V)
I/O
Standard
Min Typ Max Min Typ Max
Min
Max Min Max
Min Max
LVDS
2.375 2.5 2.625 0.1
—
—
0.65
—
0.1
—
—
—
2.0
—
—
—
—
—
—
—
—
—
Mini-LVDS 2.375 2.5 2.625
—
(2)
RSDS (2)
2.375 2.5 2.625
—
—
—
—
—
—
—
—
—
—
0
—
—
—
LVPECL
3.135 3.3 3.465 0.1
0.6
0.95
2.2
2.1
2.88
(3) (6)
Differential 1.425 1.5 1.575 0.2
1.5-V HSTL
class I
—
—
—
—
VCCIO 0.68
+ 0.6
—
0.9
—
—
—
—
VREF VREF
– 0.20 + 0.20
—
—
—
—
and II (4)
Differential
1.8-V HSTL
class I
1.71
1.8 1.89
—
—
—
—
—
VREF VREF
– 0.20 + 0.20
and II (4)
Differential 2.375 2.5 2.625 0.36
SSTL-2
class I
VCCIO 0.5 × 0.5 × 0.5 ×
VCCIO VCCIO VCCIO
– 0.2 + 0.2
VREF VREF
– 0.35 + 0.35
+ 0.6
and II (5)
Differential
SSTL-18
class I
1.7
1.8
1.9
0.25
VCCIO 0.5 × 0.5 × 0.5 ×
VCCIO VCCIO VCCIO
– 0.2 + 0.2
VREF VREF
– 0.25 + 0.25
+ 0.6
and II (5)
Notes to Table 5–8:
(1) Refer to the High-Speed Differential Interfaces in Cyclone II Devices chapter of the Cyclone II Device Handbook for
measurement conditions on VID
(2) The RSDS and mini-LVDS I/O standards are only supported on output pins.
.
(3) The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
pins.
(4) The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
pins.
(5) The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
pins.
(6) The LVPECL clock inputs are powered by VCCINT and support all VCCIO settings. However, it is recommended to
connect VCCIO to typical value of 3.3V.
Altera Corporation
February 2008
5–9
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
