DC Characteristics and Timing Specifications
Figure 5–10. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
DFF
D
PRN
Q
INPUT
VCC
clk
GND
CLRN
1
0
output
V
CC DFF
PRN
D
Q
CLRN
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–55 through 5–58 give the maximum DCD in absolution
derivation for different I/O standards on Cyclone II devices. Examples
are also provided that show how to calculate DCD as a percentage.
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins Notes (1), (2) (Part 1 of 2)
Row I/O Output Standard
C6
C7
C8
Unit
LVCMOS
165
195
120
115
130
60
230
255
120
115
130
90
230
255
135
175
135
90
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
LVTTL
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-15 Class I
HSTL-18 Class I
65
75
75
90
165
145
155
165
205
155
145
85
Altera Corporation
February 2008
5–69
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
