Global Clock Network & Phase-Locked Loops
Figure 2–15. LAB & I/O Clock Regions
Column I/O Clock Region
IO_CLK[5..0]
6
I/O Clock Regions
Cyclone Logic Array
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
6
6
6
6
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
Global Clock
Network
Row I/O Clock
Region
8 or 16
IO_CLK[5..0]
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
6
6
I/O Clock Regions
6
Column I/O Clock Region
IO_CLK[5..0]
f
For more information on the global clock network and the clock control
block, see the PLLs in Cyclone II Devices chapter in Volume 1 of the
Cyclone II Device Handbook.
2–24
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
ALTERA [ ALTERA CORPORATION ]
