DC Characteristics and Timing Specifications
Figure 5–4. High-Speed I/O Timing Budget
Note (1)
Internal Clock Period
0.5 × TCCS RSKM
SW
RSKM
0.5 × TCCS
Note to Figure 5–4:
(1) The equation for the high-speed I/O timing budget is:
period = TCCS + RSKM + SW + RSKM.
Table 5–48 shows the RSDS timing budget for Cyclone II devices at
311 Mbps. RSDS is supported for transmitting from Cyclone II devices.
Cyclone II devices cannot receive RSDS data because the devices are
intended for applications where they will be driving display drivers.
Cyclone II devices support a maximum RSDS data rate of 311 Mbps using
DDIO registers. Cyclone II devices support RSDS only in the commercial
temperature range.
Table 5–48. RSDS Transmitter Timing Specification (Part 1 of 2)
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Symbol
Conditions
Unit
Min Typ Max(1) Min Typ Max(1) Min Typ Max(1)
fHSCLK
(input
clock
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
10
10
10
10
10
10
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
10
10
10
10
10
10
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
10
10
10
10
10
10
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
311
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
frequency)
Device
operation
in Mbps
311
311
311
311
311
311
311
311
311
311
311
311
311
311
311
311
311
311
tDUTY
55
55
55
Altera Corporation
February 2008
5–57
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
