Timing Specifications
Table 5–43. Cyclone II I/O Output Delay for Row Pins (Part 4 of 4)
Fast Corner
–7
–7
–6
Speed
Grade
–8
Drive
Strength
Speed Speed
Grade Grade
(2)
Industrial
/Auto-
I/O Standard
Parameter
Speed Unit
Grade
Commer-
cial
(3)
motive
LVDS
—
—
—
—
—
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1216
1340
1216
1340
1216
1340
989
1275
1407
1275
1407
1275
1407
1036
1168
1036
1168
2089
2297
2089
2297
2089
2297
2070
2278
2070
2278
2184
2421
2184
2421
2184
2421
2214
2451
2214
2451
2272
2545
2272
2545
2272
2545
2352
2625
2352
2625
2278
2545
2278
2545
2278
2545
2358
2625
2358
2625
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
RSDS
MINI_LVDS
PCI
1113
989
PCI-X
1113
Notes to Table 5–43:
(1) This is the default setting in the Quartus II software.
(2) These numbers are for commercial devices.
(3) These numbers are for automotive devices.
Maximum Input and Output Clock Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–44 specifies the maximum input clock toggle rates. Table 5–45
specifies the maximum output clock toggle rates at default load.
Table 5–46 specifies the derating factors for the output clock toggle rate
for non-default load.
To calculate the output toggle rate for a non-default load, use this
formula:
The toggle rate for a non-default load
5–46
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
ALTERA [ ALTERA CORPORATION ]
