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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration & Testing  
Table 3–1. Cyclone II JTAG Instructions (Part 2 of 2)  
JTAG Instruction  
Instruction Code  
Description  
Allows configuration of I/O standards through the JTAG chain for  
JTAG testing. Can be executed before, after, or during  
configuration. Stops configuration if executed during configuration.  
Once issued, the CONFIG_IOinstruction holds nSTATUSlow to  
reset the configuration device. nSTATUSis held low until the  
device is reconfigured.  
CONFIG_IO  
00 0000 1101  
SignalTap II  
instructions  
Monitors internal device operation with the SignalTap II embedded  
logic analyzer.  
Note to Table 3–1:  
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.  
The Quartus II software has an Auto Usercode feature where you can  
choose to use the checksum value of a programming file as the JTAG user  
code. If selected, the checksum is automatically loaded to the USERCODE  
register. In the Settings dialog box in the Assignments menu, click Device  
& Pin Options, then General, and then turn on the Auto Usercode  
option.  
Altera Corporation  
February 2007  
3–3  
Cyclone II Device Handbook, Volume 1  
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