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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Timing Specifications  
Table 5–50. LVDS Transmitter Timing Specification (Part 2 of 2)  
–6 Speed Grade  
–7 Speed Grade  
–8 Speed Grade  
Symbol Conditions  
Unit  
Max Max  
Max Max  
Max Max  
Min  
Typ  
Min  
Typ  
Min  
Typ  
(1)  
(2)  
(1)  
(2)  
(1)  
(2)  
80–20%  
150  
200  
250  
100  
150  
200  
250  
100  
150  
200  
ps  
tFALL  
250 (11)  
100 (12)  
μs  
tLOCK  
Notes to Table 5–50:  
(1) The maximum data rate that complies with duty cycle distortion of 45–55%.  
(2) The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with 45–55%  
duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45–55% range, you  
may use the higher data rate values from this column. You can calculate the duty cycle distortion as a percentage  
using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1562.5 ps) and a tDU TY of 250 ps, the  
duty cycle distortion is tDU TY/(UI*2) *100% = 250 ps/(1562.5 *2) * 100% = 8%, which gives you a duty cycle  
distortion of 42–58%.  
(3) The TCCS specification applies to the entire bank of LVDS, as long as the SERDES logic is placed within the LAB  
adjacent to the output pins.  
(4) For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 137.5 MHz.  
(5) For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 275 Mbps.  
(6) For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 200 MHz.  
(7) For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 400 Mbps.  
(8) For extended temperature devices, the maximum input clock frequency for ×1 mode is 340 MHz.  
(9) For extended temperature devices, the maximum data rate for ×1 mode is 340 Mbps.  
(10) For extended temperature devices, the maximum output jitter (peak to peak) is 600 ps.  
(11) For extended temperature devices, the maximum tRIS E and tFALL are 300 ps.  
(12) For extended temperature devices, the maximum lock time is 500 us.  
5–62  
Altera Corporation  
February 2008  
Cyclone II Device Handbook, Volume 1  
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