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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

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型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Timing Specifications  
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 2 of 2)  
–6 Speed Grade  
–7 Speed Grade  
–8 Speed Grade  
Symbol  
Conditions  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Min  
Typ  
Max  
Device  
operation  
in Mbps  
×10  
×8  
×7  
×4  
×2  
×1  
100  
80  
70  
40  
20  
10  
45  
311  
311  
311  
311  
311  
311  
55  
100  
80  
70  
40  
20  
10  
45  
311  
311  
311  
311  
311  
311  
55  
100  
80  
70  
40  
20  
10  
45  
311  
311  
311  
311  
311  
311  
55  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
tDUTY  
TCCS  
200  
500  
200  
500  
200  
500  
ps  
Output  
ps  
jitter (peak  
to peak)  
tRISE  
tFALL  
tLOCK  
20–80%  
80–20%  
500  
500  
100  
500  
500  
100  
500  
500  
100  
ps  
ps  
μs  
In order to determine the transmitter timing requirements, mini-LVDS  
receiver timing requirements on the other end of the link must be taken  
into consideration. The mini-LVDS receiver timing parameters are  
typically defined as tSU and tH requirements. Therefore, the transmitter  
timing parameter specifications are tCO (minimum) and tCO (maximum).  
Refer to Figure 5–4 for the timing budget.  
The AC timing requirements for mini-LVDS are shown in Figure 5–6.  
Figure 5–6. mini-LVDS Transmitter AC Timing Specification  
TUI  
LVDSCLK[]n  
LVDSCLK[]p  
t
(1)  
t
(2)  
t
(1)  
t (2)  
H
SU  
H
SU  
LVDS[]p  
LVDS[]n  
Notes to Figure 5–6:  
(1) The data setup time, tSU, is 0.225 × TUI.  
(2) The data hold time, tH, is 0.225 × TUI.  
5–60  
Altera Corporation  
February 2008  
Cyclone II Device Handbook, Volume 1  
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