Configuration & Testing
Cyclone II devices support the SignalTap II embedded logic analyzer,
which monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA®
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
SignalTap II
Embedded Logic
Analyzer
f
For more information on the SignalTap II, see the Signal Tap chapter of
the Quartus II Handbook, Volume 3.
The logic, circuitry, and interconnects in the Cyclone II architecture are
configured with CMOS SRAM elements. Altera FPGA devices are
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Configuration
Cyclone II devices are configured at system power-up with data stored in
an Altera configuration device or provided by a system controller. The
Cyclone II device’s optimized interface allows the device to act as
controller in an active serial configuration scheme with EPCS serial
configuration devices. The serial configuration device can be
programmed via SRunner, the ByteBlaster II or USB Blaster download
cable, the Altera Programming Unit (APU), or third-party programmers.
In addition to EPCS serial configuration devices, Altera offers in-system
programmability (ISP)-capable configuration devices that can configure
Cyclone II devices via a serial data stream using the Passive serial (PS)
configuration mode. The PS interface also enables microprocessors to
treat Cyclone II devices as memory and configure them by writing to a
virtual memory location, simplifying reconfiguration. After a Cyclone II
device has been configured, it can be reconfigured in-circuit by resetting
the device and loading new configuration data. Real-time changes can be
made during system operation, enabling innovative reconfigurable
applications.
The Cyclone II architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. You can use the 10MHz internal oscillator or the
optional CLKUSRpin during the initialization. The 10 MHz internal
oscillator is disabled in user mode. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
Operating
Modes
Altera Corporation
February 2007
3–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
