Embedded Multipliers
Figure 2–18. Multiplier Block Architecture
signa (1)
signb (1)
aclr
clock
ena
D
Q
Q
Data A
Data B
ENA
Data Out
D
Q
CLRN
ENA
CLRN
D
ENA
Output
Register
Input
Register
CLRN
Embedded Multiplier Block
Note to Figure 2–18:
(1) If necessary, these signals can be registered once to match the data signal path.
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signa and signb, control the representation of each
operand respectively. A logic 1 value on the signa signal indicates that
data A is a signed number while a logic 0 value indicates an unsigned
number. Table 2–11 shows the sign of the multiplication result for the
various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.
Table 2–11. Multiplier Sign Representation
Data A (signa Value)
Data B (signb Value)
Result
Unsigned
Unsigned
Signed
Unsigned
Signed
Unsigned
Signed
Signed
Signed
Unsigned
Signed
Signed
2–34
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007
ALTERA [ ALTERA CORPORATION ]
