Cyclone II Architecture
Figure 2–2 shows a Cyclone II LE.
Figure 2–2. Cyclone II LE
Register Chain
Routing From
Previous LE
LAB-Wide
Register Bypass
Packed
Synchronous
LAB Carry-In
Load
Programmable
Register
LAB-Wide
Synchronous
Clear
Register Select
data1
data2
data3
Row, Column,
And Direct Link
Routing
Synchronous
Load and
Clear Logic
Look-Up
Table
(LUT)
Carry
Chain
D
Q
data4
ENA
CLRN
Row, Column,
And Direct Link
Routing
labclr1
labclr2
Asynchronous
Clear Logic
Local Routing
Chip-Wide
Reset
(DEV_CLRn)
Register Chain
Output
Clock &
Clock Enable
Select
Register
Feedback
labclk1
labclk2
labclkena1
labclkena2
LAB Carry-Out
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinational functions, the LUT output bypasses the
register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources, allowing
the LUT to drive one output while the register drives another output. This
feature, register packing, improves device utilization because the device
can use the register and the LUT for unrelated functions. When using
register packing, the LAB-wide synchronous load control signal is not
available. See “LAB Control Signals” on page 2–8 for more information.
Altera Corporation
February 2007
2–3
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
