Hot Socketing & Power-On Reset
the power supply can provide current to the device’s VCC and ground
planes. This condition can lead to latch-up and cause a low-impedance
path from VCC to ground within the device. As a result, the device extends
a large amount of current, possibly causing electrical damage.
Altera has ensured by design of the I/O buffers and hot-socketing
circuitry, that Cyclone II devices are immune to latch-up during hot
socketing.
The hot-socketing feature turns off the output buffer during power up
(either VCCINT or VCCIO supplies) or power down. The hot-socket circuit
generates an internal HOTSCKTsignal when either VCCINT or VCCIO is
below the threshold voltage. Designs cannot use the HOTSCKTsignal for
other purposes. The HOTSCKTsignal cuts off the output buffer to ensure
that no DC current (except for weak pull-up leakage current) leaks
through the pin. When VCC ramps up slowly, VCC is still relatively low
even after the internal PORsignal (not available to the FPGA fabric used
by customer designs) is released and the configuration is finished. The
CONF_DONE, nCEO, and nSTATUSpins fail to respond, as the output
buffer cannot drive out because the hot-socketing circuitry keeps the I/O
pins tristated at this low VCC voltage. Therefore, the hot-socketing circuit
has been removed on these configuration output or bidirectional pins to
ensure that they are able to operate during configuration. These pins are
expected to drive out during power-up and power-down sequences.
Hot-Socketing
Feature
Implementation
in Cyclone II
Devices
Each I/O pin has the circuitry shown in Figure 4–1.
Altera Corporation
February 2007
4–3
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
