Global Clock Network & Phase-Locked Loops
Figure 2–11. EP2C5 & EP2C8 PLL, CLK[], DPCLK[] & Clock Control Block Locations
DPCLK10
DPCLK8
PLL 2
Clock Control
Block (1)
GCLK[7..0]
4
DPCLK0
DPCLK7
CLK[7..4]
DPCLK6
8
8
8
CLK[3..0]
DPCLK1
4
4
8
GCLK[7..0]
4
Clock Control
Block (1)
PLL 1
DPCLK2
DPCLK4
Note to Figure 2–11:
(1) There are four clock control blocks on each side.
2–18
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1