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EP2C8F256C6N 参数 Datasheet PDF下载

EP2C8F256C6N图片预览
型号: EP2C8F256C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 516 CLBs, 500MHz, 8256-Cell, CMOS, PBGA256, LEAD FREE, FBGA-256]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 168 页 / 956 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone II Architecture  
PLLs  
Cyclone II PLLs provide general-purpose clocking as well as support for  
the following features:  
Clock multiplication and division  
Phase shifting  
Programmable duty cycle  
Up to three internal clock outputs  
One dedicated external clock output  
Clock outputs for differential I/O support  
Manual clock switchover  
Gated lock signal  
Three different clock feedback modes  
Control signals  
Cyclone II devices contain either two or four PLLs. Table 2–3 shows the  
PLLs available for each Cyclone II device.  
Table 2–3. Cyclone II Device PLL Availability  
Device  
PLL1  
PLL2  
PLL3  
PLL4  
EP2C5  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
EP2C8  
EP2C15  
EP2C20  
EP2C35  
EP2C50  
EP2C70  
v
v
v
v
v
v
v
v
v
v
Altera Corporation  
February 2007  
2–25  
Cyclone II Device Handbook, Volume 1  
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