External Memory Interface Standards
Figure 9–1. Example of a 90° Shift on the DQS Signal
Notes (1), (2)
DQS pin to
egister delay
r
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
(3)
DQS at
IOE registers
90˚ degree
DQ at
IOE registers
DQ pin to
egister delay
r
Notes to Figure 9–1:
(1) RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
(2) DDR2 SDRAM does not support a burst length of two.
(3) The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
must send the data strobe to the memory device center-aligned relative to
the data. Cyclone II devices use a PLL to center-align the data strobe by
generating a 0° phase-shifted system clock for the write data strobes and
a –90° phase-shifted write clock for the write data pins for the DDR and
DDR2 SDRAM. Figure 9–2 shows an example of the relationship between
the data and data strobe during a burst-of-two write.
Figure 9–2. DQ & DQS Relationship During a DDR & DDR2 SDRAM Write
DQS at
FPGA Pin
DQ at
FPGA Pin
9–4
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
