Cyclone II Memory Blocks
Table 8–8 shows the revision history for this document.
Document
Revision History
Table 8–8. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
February 2008
v2.4
Corrected Figure 8–12.
—
February 2007
v2.3
●
●
●
Added document revision history.
●
●
In packed mode support,
the maximum data width for
each of the two memory
block is 18 bits wide.
Added don’t care mode
information to mixed-port
read-during-write mode
section.
Updated “Packed Mode Support” section.
Updated “Mixed-Port Read-During-Write Mode” section
and added new Figure 8–24.
November 2005 Updated Figures 8–13 through 8–20.
v2.1
—
July 2005 v2.0
Added Clear Signals section.
—
—
February 2005
v1.1
Added a note to Figures 8-13 through 8-20 regarding
violating the setup and hold time on address registers.
June 2004 v1.0 Added document to the Cyclone II Device Handbook.
—
Altera Corporation
February 2008
8–31
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
