PLLs in Cyclone II Devices
ΔtFINE periods. OUTCLK2is based off the 0° phase from the VCO but has
the S value for the counter set to 3. This creates a delay of two ΔtCOARSE
periods.
Figure 7–8. Cyclone II PLL Phase Shifting using VCO Phase Output & Counter Delay Time
1/8 t
t
VCO
VCO
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
OUTCLK0
t
d0-1
OUTCLK1
OUTCLK2
t
d0-2
Control Signals
The four control signals in Cyclone II PLLs (pllena, areset, pfdena,
and locked) control PLL operation.
pllena
The PLL enable signal, pllena, enables and disables the PLL. You can
either enable/disable a single PLL (by connecting pllenaport
independently) or multiple PLLs (by connecting pllenaports together).
The pllenasignal is an active-high signal. When pllenais low, the PLL
clock output ports are driven by GND and the PLL loses lock. All PLL
counters, including gated lock counter return to default state. When
pllenatransitions high, the PLL relocks and resynchronizes to the input
clock. In Cyclone II devices, the pllenaport can be fed by an LE output
or any general-purpose I/O pin. There is no dedicated pllenapin. This
increases flexibility since each PLL can have its own pllenacontrol
circuitry or all PLLs can share the same pllenacircuitry. The pllena
signal is optional. When it is not enabled in the Quartus II software, the
port is internally tied to VCC
.
Altera Corporation
February 2007
7–17
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
