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EP2C20F256C8N 参数 Datasheet PDF下载

EP2C20F256C8N图片预览
型号: EP2C20F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 可编程逻辑PC时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Supported I/O Standards  
Figure 10–15. 1.5-V Differential HSTL Class I Termination  
VTT = 0.75 V  
VTT = 0.75 V  
Differential  
Transmitter  
Differential  
Receiver  
50 Ω  
50 Ω  
Z
= 50 Ω  
= 50 Ω  
0
Z
0
Figure 10–16. 1.5-V Differential HSTL Class II Termination  
VTT = 0.75 V  
VTT = 0.75 V  
VTT = 0.75 V  
VTT = 0.75 V  
Differential  
Transmitter  
Differential  
Receiver  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
Z
= 50 Ω  
0
Z
= 50 Ω  
0
LVDS, RSDS and mini-LVDS  
The LVDS standard is formulated under ANSI/TIA/EIA Standard,  
ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage  
Differential Signaling Interface Circuits.  
The LVDS I/O standard is a differential high-speed, low-voltage swing,  
low-power, general-purpose I/O interface standard. This standard is  
used in applications requiring high-bandwidth data transfer, backplane  
drivers, and clock distribution. Cyclone II devices are capable of running  
at a maximum data rate of 805 Mbps for input and 640 Mbps for output  
and still meet the ANSI/TIA/EIA-644 standard.  
Because of the low voltage swing of the LVDS I/O standard, the  
electromagnetic interference (EMI) effects are much smaller than  
complementary metal-oxide semiconductor (CMOS),  
10–16  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2008