Selectable I/O Standards in Cyclone II Devices
Figure 10–6. 1.8-V SSTL Class II Termination
V
= 0.9 V
V
= 0.9 V
TT
TT
Output Buffer
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
25 Ω
V
= 0.9 V
REF
1.8-V HSTL Class I and II
The HSTL standard is a technology independent I/O standard developed
by JEDEC to provide voltage scalability. It is used for applications
designed to operate in the 0.0- to 1.8-V HSTL logic switching range such
as quad data rate (QDR) memory clock interfaces.
Although JEDEC specifies a maximum VCCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a VCCIO
of 1.8 V. Cyclone II devices support interfaces with VCCIO of 1.8 V for
HSTL. Figures 10–7 and 10–8 show the nominal VREF and VTT required to
track the higher value of VCCIO. The value of VREF is selected to provide
optimum noise margin in the system. Cyclone II devices support both
input and output levels of operation.
Figure 10–7. 1.8-V HSTL Class I Termination
V
= 0.9 V
TT
Output Buffer
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.9 V
REF
Figure 10–8. 1.8-V HSTL Class II Termination
V
= 0.9 V
V
= 0.9 V
TT
TT
Output Buffer
50 Ω
50 Ω
Input Buffer
Z = 50 Ω
V
= 0.9 V
REF
Altera Corporation
February 2008
10–11
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
