External Memory Interfaces
Figure 9–16. Bidirectional DDR Implementation for DDR Memory Interfaces Note (1)
OE
datain_h
LE
Register
data1
data0
Output Register AO
sel
datain_l
LE
Register
TRI
Output Register BO
outclk
DQ
dataout_h
LE
LE
Register
Register
sync_reg_h
Input Register AI
neg_reg_out
dataout_l
LE
LE
LE
Register
Register
Register
Clock Delay
Control Circuitry
sync_reg_l
Register CI
Input Register BI
resynch_clk
DQS
t
VCC
LE
Register
TRI
sel
GND
LE
Register
Note to Figure 9–16:
(1) You can use the altdqand altdqsmegafunctions to generate the DQ and DQS signals.
Figure 9–17 shows example waveforms from a bidirectional DDR
implementation.
Altera Corporation
February 2007
9–23
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
