EP220 & EP224
Classic EPLDs
®
May 1995, ver. 1
Data Sheet
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High-performance, low-power Erasable Programmable Logic
Devices (EPLDs) with 8 macrocells
Features
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Combinatorial speeds as low as 7.5 ns
Counter frequencies of up to 100 MHz
Pipelined data rates of up to 115 MHz
Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup
time
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Replacement or upgrade for 16V8/20V8 PAL and GAL devices
Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14
dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224
Macrocells independently programmable for both registered and
combinatorial logic
Programmable inversion control supporting active-high or active-
low outputs
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Low power consumption
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Typical I = 90 mA at 25 MHz (for -7A speed grades)
CC
Quarter-power mode (I = 40 mA)
CC
Programmable zero-power mode with typical I = 50 µA
CC
(for -10A and -12 speed grades)
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Programmable Security Bit for total protection of proprietary designs
Low output skew for Clock driver applications
100% generically tested to provide 100% programming yield
Software and programming support from Altera and a wide range of
third-party tools
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Available in windowed ceramic and one-time-programmable (OTP)
plastic packages
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20-pin plastic J-lead package (PLCC)
20-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
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24-pin PDIP
28-pin PLCC
The EPROM-based EP220 and EP224 devices feature a flexible I/O
architecture and implement 150 usable (300 available) gates of custom
user logic functions. EP220 and EP224 devices can be used as upgrades for
high-speed bipolar programmable logic devices (PLDs) or for 74-series LS
and CMOS (SSI and MSI) logic devices in high-performance
microcomputer systems.
General
Description
Altera Corporation
1
A-ds-220/224-01
ALTERA [ ALTERA CORPORATION ]
