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EP220-12 参数 Datasheet PDF下载

EP220-12图片预览
型号: EP220-12
PDF下载: 下载PDF文件 查看货源
内容描述: 经典EPLD中 [Classic EPLDs]
分类和应用:
文件页数/大小: 16 页 / 400 K
品牌: ALTERA [ ALTERA CORPORATION ]
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EP220 & EP224 Classic EPLDs  
Figure 1. EP220 & EP224 Block Diagram  
Numbers in parentheses refer to the pin-out number.  
EP220  
Global Clock  
INPUT/CLK  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(11)  
I/O (19)  
I/O (18)  
I/O (17)  
I/O (16)  
I/O (15)  
I/O (14)  
I/O (13)  
I/O (12)  
Macrocell 1  
Macrocell 2  
Macrocell 3  
Macrocell 4  
Macrocell 5  
Macrocell 6  
Macrocell 7  
Macrocell 8  
Global  
Bus  
EP224  
Global Clock  
INPUT/CLK  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
INPUT  
(1)  
(2)  
(3)  
(4)  
I/O (22)  
I/O (21)  
I/O (20)  
I/O (19)  
I/O (18)  
I/O (17)  
I/O (16)  
I/O (15)  
Macrocell 1  
Macrocell 2  
Macrocell 3  
Macrocell 4  
Macrocell 5  
Macrocell 6  
Macrocell 7  
Macrocell 8  
(5)  
(6)  
(7)  
Global  
Bus  
(8)  
(9)  
(10)  
(11)  
(13)  
(14)  
(23)  
The EP220 and EP224 architecture is based on a sum-of-products,  
programmable-AND/fixed-ORstructure. Each macrocell can be  
individually programmed for combinatorial or registered output. An  
inversion option allows each output to be configured for active-high or  
active-low operation. Each I/O pin can be programmed to function as an  
input, output, or bidirectional pin.  
The EP220 and EP224 device architecture offers the following features:  
Macrocells  
High-frequency, low-skew global Clock  
Altera Corporation  
3