DC & Switching Characteristics
Table 6–52 shows the external I/O timing parameters when using
regional clock networks.
Table 6–52. Stratix GX Regional Clock External I/O Timing Parameters
Notes (1), (2)
Conditions
Symbol
Parameter
tINSU
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by CLK pin
tINH
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by CLK pin
tOUTCO
Clock-to-output delay output or bidirectional pin using
CLOAD = 10 pF
column IOE output register with regional clock fed by CLK
pin
tINSUPLL
Setup time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
tINHPLL
Hold time for input or bidirectional pin using column IOE
input register with regional clock fed by Enhanced PLL with
default phase setting
tOUTCOPLL
Clock-to-output delay output or bidirectional pin using
column IOE output register with regional clock Enhanced
PLL with default phase setting
CLOAD = 10 pF
Notes to Table 6–52:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column IOE pins. Row IOE pins are 100- to 250-ps slower depending on device,
speed grade, and the specific parameter in question. You should use the Quartus II software to verify the external
timing for any pin.
Table 6–53 shows the external I/O timing parameters when using global
clock networks.
Table 6–53. Stratix GX Global Clock External I/O Timing Parameters (Part 1 of 2)
Notes (1), (2)
Symbol
Parameter
Conditions
tINSU
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by CLK pin
tINH
Hold time for input or bidirectional pin using column IOE
input register with global clock fed by CLK pin
tOUTCO
tINSUPLL
Clock-to-output delay output or bidirectional pin using
column IOE output register with global clock fed by CLK pin
CLOAD = 10 pF
Setup time for input or bidirectional pin using column IOE
input register with global clock fed by Enhanced PLL with
default phase setting
Altera Corporation
August 2005
6–37
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
