DC & Switching Characteristics
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 2 of 7)
-6 Commercial &
-7 Commercial &
Industrial Speed
-5 Commercial
Speed Grade (1)
Industrial Speed
Symbol /
Description
Grade
Grade
(1)
Conditions
Unit
(1)
Min Typ
Max
Min Typ
Max
Min Typ
Max
20
Reference Clock
Jitter
Jitter
components
<20 MHz
20
20
ps
ps
tolerance
(peak-to-
peak)
Wideband
50
50
50
Reference
input clock
frequency
Dedicated
refclkb pins
25
25
650
25
25
650
25
25
312.5 MHz
PLD clock
resources
325
325
156.25 MHz
Receiver
Serial data
rate
(general)
Commercial /
industrial
614
500
20
3,187.5 614
3,187.5 500
3,187.5 614
3,187.5 500
2,500 Mbps
2,500 Mbps
312.5 MHz
Serial data
rate (8B/10B industrial
encoded)
Commercial /
Parallel
398.4
100
20
375
100
20
transceiver/
logic array
interface
speed
Rate
XAUI mode only
100
ppm
matching
frequency
tolerance
8B/10B Custom Receiver Jitter Tolerance using Encoded CJPAT
Note (2)
Deterministic 500 Mbps
jitter
0.45
0.45
0.45
0.71
UI
UI
Total jitter
500 Mbps
0.71
0.71
Fibre Channel Receiver Jitter Tolerance using 8B/10B Encoded CJTPAT
Note (2)
Deterministic 1.0625 Gbps
jitter
0.37
0.37
0.37
0.68
UI
UI
Total jitter
1.0625 Gbps
0.68
0.68
Altera Corporation
August 2005
6–5
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
