I/O Structure
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 4–64 shows an IOE configured for DDR input. Figure 4–65 shows
the DDR input timing diagram.
Figure 4–64. Stratix GX IOE in DDR Input I/O Configuration
Note (1)
VCCIO
Column or Row
Interconnect
ioe_clk[7..0]
(1)
Optional
To DQS Local
Bus (3)
PCI Clamp
I/O Interconnect DQS Local
[15..0] Bus (1), (2)
(1)
VCCIO
Programmable
Pull-Up
Resistor
Input Pin to
Input Register Delay
sclr
Input Register
D
Q
clkin
ENA
CLRN/PRN
Output Clock
Enable Delay
Bus-Hold
Circuit
aclr/prn
Chip-Wide Reset
Latch
D Q
Input Register
D
Q
ENA
ENA
CLRN/PRN
CLRN/PRN
Notes to Figure 4–64:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
4–104
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
