PLLs & Clock Networks
Figure 4–57. Stratix GX Device Fast PLL
Post-Scale
Counters
diffioclk1 (2)
Global or
÷l0
regional clock
txload_en
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
rxload_en
÷l1
Global or
regional clock
Global or
regional clock (1)
diffioclk2 (2)
8
Charge
Pump
Loop
Filter
Global or
regional clock
÷g0
PFD
VCO
Clock
Input
m÷
Notes to Figure 4–57:
(1) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(2) This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
The Stratix GX device’s fast PLLs provide clock synthesis for PLL output
ports using m/(post scaler) scaling factors. The input clock is multiplied
by the m feedback factor. Each output port has a unique post scale counter
to divide down the high-frequency VCO. There is one multiply divider,
m, per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed differential interface, you can set the output
counter to 1 to allow the high-speed VCO frequency to drive the SERDES.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or for general-purpose external clocks.
There are no dedicated external clock output pins. Any I/O pin can be
driven by the fast PLL global or regional outputs as an external output
4–94
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
