Stratix GX Architecture
Clock Multiplication & Division
Each Stratix GX device enhanced PLL provides clock synthesis for PLL
output ports using m/(n × post-scale counter) scaling factors. The input
clock is divided by a pre-scale divider, n, and is then multiplied by the m
feedback factor. The control loop drives the VCO to match fIN × (m/n).
Each output port has a unique post-scale counter that divides down the
high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output
frequencies that meets its frequency specifications. Then, the post-scale
dividers scale down the output frequency for each output port. For
example, if output frequencies required from one PLL are 33 and 66 MHz,
set the VCO to 330 MHz (the least common multiple in the VCO’s range).
There is one pre-scale divider, n, and one multiply divider, m, per PLL,
with a range of 1 to 512 on each. There are two post-scale dividers (l) for
regional clock output ports, four counters (g) for global clock output
ports, and up to four counters (e) for external clock outputs, all ranging
from 1 to 512. The Quartus II software automatically chooses the
appropriate scaling factors according to the input frequency,
multiplication, and division values entered.
Clock Switchover
To effectively develop high-reliability network systems, clocking schemes
must support multiple clocks to provide redundancy. For this reason,
Stratix GX device enhanced PLLs support a flexible clock switchover
capability. Figure 4–52 shows a block diagram of the switchover
circuit.The switchover circuit is configurable, so you can define how to
implement it. Clock-sense circuitry automatically switches from the
primary to secondary clock for PLL reference when the primary clock
signal is not present.
Altera Corporation
February 2005
4–83
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
