PLLs & Clock Networks
Table 4–18. Stratix GX Enhanced PLL & Fast PLL Features (Part 2 of 2)
Notes (1)–(8)
Fast PLL
Feature
Enhanced PLL
Number of external clock outputs
Four differential/eight singled-ended
(7)
or one single-ended (6)
Number of feedback clock inputs
4 (8)
Notes to Table 4–18:
(1) The maximum count value is 1024, with a 50% duty cycle setting on the counter. The maximum count value for
any other duty cycle setting is 512.
(2) For fast PLLs, m and post-scale counters range from 1 to 32.
(3) The smallest phase shift is determined by the VCO period divided by 8.
(4) For degree increments, Stratix GX devices can shift all output frequencies in increments of at least 45°. Smaller
degree increments are possible depending on the frequency and divide parameters.
(5) PLLs 7 and 8 have two output ports per PLL. PLLs 1 and 2 have three output ports per PLL.
(6) Every Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with eight single-ended or four differential outputs
each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1SGX40 devices each have one single-ended output.
(7) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
(8) Every Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per
PLL.
Figure 4–48 shows a top-level diagram of the Stratix GX device and the
PLL floorplan.
4–78
Altera Corporation
February 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
