Stratix Architecture
clock signals are routed from LAB row clocks and are generated from
specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in Table 2–17.
Table 2–17. DSP Block Signal Sources & Destinations
LAB Row at
Interface
Control Signals
Generated
Data Inputs
Data Outputs
1
2
signa
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
aclr0
accum_sload0
3
4
5
6
addnsub1
clock0
ena0
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
aclr1
clock1
ena1
aclr2
clock2
ena2
sign_b
clock3
ena3
7
8
clear3
accum_sload1
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
addnsub3
Stratix devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
PLLs & Clock
Networks
Global & Hierarchical Clocking
Stratix devices provide 16 dedicated global clock networks, 16 regional
clock networks (four per device quadrant), and 8 dedicated fast regional
clock networks (for EP1S10, EP1S20, and EP1S25 devices), and
16 dedicated fast regional clock networks (for EP1S30 EP1S40, and
EP1S60, and EP1S80 devices). These clocks are organized into a
hierarchical clock structure that allows for up to 22 clocks per device
region with low skew and delay. This hierarchical clocking scheme
provides up to 48 unique clock domains within Stratix devices.
Altera Corporation
July 2005
2–73
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
