Stratix Architecture
Figure 2–22. M-RAM Row Unit Interface to Interconnect
C4 and C8 Interconnects
R4 and R8 Interconnects
M-RAM Block
LAB
10
Direct Link
Interconnects
addressa
addressb
renwe_a
renwe_b
Up to 24
byteena [ ]
A
byteena [ ]
B
clocken_a
clocken_b
clock_a
clock_b
aclr_a
aclr_b
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Altera Corporation
July 2005
2–41
Stratix Device Handbook, Volume 1