TriMatrix Memory
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
M512 RAM Block M4K RAM Block M-RAM Block
(32 × 18 Bits) (128 × 36 Bits) (4K × 144 Bits)
Memory Feature
Configurations
512 × 1
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
Notes to Table 2–3:
(1) See Table 4–36 for maximum performance information.
(2) The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix device must write to the dual-port memory once and then disable the
write-enable ports afterwards.
1
Violating the setup or hold time on the address registers could
corrupt the memory contents. This applies to both read and
write operations.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 2–12 shows true dual-port memory.
Figure 2–12. True Dual-Port Memory Configuration
A
B
dataA[]
dataB[]
addressA[]
wrenA
addressB[]
wrenB
clockA
clockenA
qA[]
clockB
clockenB
qB[]
aclrA
aclrB
2–22
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
