Stratix Device Handbook, Volume 1
I/O Standards 4–5
Row I/O Block Connection to the
Interconnect 2–106
M
Memory Architecture
Byte Enable for M4K
RAM Block
Row Pin
Input Delay Adders 4–67
Signal Path through the I/O Block 2–108
SSTL-18 4–11
SSTL-2 4–12
SSTL-3 4–12, 4–13
2–32
Byte Enable for M-RAM
Block
2–35
External RAM Interfacing 2–115
M4K
Stratix IOE in Bidirectional I/O
Configuration 2–110
Block Internal Timing
Microparameter
Descriptions 4–24
Microparameters 4–31
RAM Block
Supported I/O Standards 2–123
Transmitter Output Waveforms for Differ-
ential I/O Standards 4–6
Interconnect
C4 Connections 2–18
DSP Block Interface to Interconnect 2–72
2–30
Configurations (Simple Dual-
Port) 2–31
Configurations
Left-Facing
M-RAM
to
Interconnect
Interface 2–40
Chain
(True
Port) 2–31
Dual-
LUT
Register
Chain
Interconnects 2–17
M-RAM
Column
Interconnect 2–42
Control Signals 2–33
LAB Row Interface 2–33
Unit
Interface
to
M512
Block Internal Timing
Microparameter
Descriptions 4–24
Microparameters 4–30
RAM Block
Architecture 2–27
Row Unit Interface to Interconnect 2–41
R4 Connections 2–15
IOE
Internal Timing Microparameters 4–29
Configurations (Simple Dual-Port
RAM) 2–27
Control Signals 2–29
LAB Row Interface 2–30
J
JTAG
Boundary-Scan
Register Length 3–3
Support 3–1
Stratix JTAG
Memory Block Size 2–26
Memory Modes 2–21
M-RAM
Block
Instructions 3–2
Waveforms 3–4
2–34
Configurations (Simple Dual-
Port) 2–34
Configurations (True
L
Dual-
LAB
Control Signals 2–5
Wide Control Signals 2–6
LUT
Port) 2–35
Block Control Signals 2–37
Block Internal Timing
Microparameter
Chain & Register Chain 2–8
Descriptions 4–25
Combined Byte Selection for x144
Altera Corporation
Index–5
ALTERA [ ALTERA CORPORATION ]
