DC & Switching Characteristics
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 2 of 2)
-6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
CTT
350
350
350
350
250
350
300
300
300
300
200
300
300
300
300
300
200
300
MHz
MHz
MHz
MHz
MHz
MHz
Differential 1.5-V HSTL
C1
LVPECL (1)
PCML (1)
LVDS (1)
645
275
645
500
622
275
622
450
622
275
622
450
MHz
MHz
MHz
MHz
HyperTransport
technology (1)
Note to Tables 4–114 through 4–119:
(1) These parameters are only available on row I/O pins.
Tables 4–120 through 4–123 show the maximum output clock rate for
column and row pins in Stratix devices.
Table 4–120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins
in Flip-Chip Packages (Part 1 of 2)
-5 Speed -6 Speed -7 Speed -8 Speed
I/O Standard
Unit
Grade
Grade
Grade
Grade
LVTTL
350
350
250
225
350
200
200
200
200
200
200
150
300
300
250
200
300
167
167
167
167
200
200
134
250
300
250
200
250
125
125
167
167
167
167
134
250
300
250
200
250
125
125
133
133
167
167
134
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I (3)
SSTL-2 Class I (4)
SSTL-2 Class I (5)
Altera Corporation
July 2005
4–81
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
