Timing Model
Tables 4–67 through 4–72 show the external timing parameters on column
and row pins for EP1S25 devices.
Table 4–67. EP1S25 External I/O Timing on Column Pins Using Fast Regional Clock Networks
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tINSU
2.412
0.000
2.196
2.136
2.136
2.613
0.000
2.196
2.136
2.136
2.968
0.000
2.196
2.136
2.136
3.468
0.000
2.196
2.136
2.136
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
4.475
4.349
4.349
4.748
4.616
4.616
5.118
4.994
4.994
5.603
5.488
5.488
tZX
Table 4–68. EP1S25 External I/O Timing on Column Pins Using Regional Clock Networks
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tINSU
1.535
0.000
2.739
2.679
2.679
0.934
0.000
1.316
1.256
1.256
1.661
0.000
2.739
2.679
2.679
0.980
0.000
1.316
1.256
1.256
1.877
0.000
2.739
2.679
2.679
1.092
0.000
1.316
1.256
1.256
2.125
0.000
2.739
2.679
2.679
1.231
0.000
1.316
1.256
1.256
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
5.396
5.270
5.270
5.746
5.614
5.614
6.262
6.138
6.138
6.946
6.831
6.831
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
2.733
2.607
2.607
2.839
2.707
2.707
2.921
2.797
2.797
3.110
2.995
2.995
tXZPLL
tZXPLL
4–42
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
