Stratix Architecture
However, there is additional resistance present between the device ball
and the input of the receiver buffer, as shown in Figure 2–72. This
resistance is because of package trace resistance (which can be calculated
as the resistance from the package ball to the pad) and the parasitic layout
metal routing resistance (which is shown between the pad and the
intersection of the on-chip termination and input buffer).
Figure 2–72. Differential Resistance of LVDS Differential Pin Pair (RD)
Pad
Package Ball
LVDS
Input Buffer
0.3 Ω
0.3 Ω
9.3 Ω
9.3 Ω
R
D
Differential On-Chip
Termination Resistor
Table 2–35 defines the specification for internal termination resistance for
commercial devices.
Table 2–35. Differential On-Chip Termination
Resistance
Symbol
Description
Conditions
Unit
Min Typ Max
RD (2)
Internal differential termination for LVDS
Commercial (1), (3)
Industrial (2), (3)
110 135 165
100 135 170
W
W
Notes to Table 2–35:
(1) Data measured over minimum conditions (Tj = 0 C, VCC IO +5%) and maximum conditions (Tj = 85 C,
VC CIO = –5%).
(2) Data measured over minimum conditions (Tj = –40 C, VCCIO +5%) and maximum conditions (Tj = 100 C,
VCCIO = –5%).
(3) LVDS data rate is supported for 840 Mbps using internal differential termination.
MultiVolt I/O Interface
The Stratix architecture supports the MultiVolt I/O interface feature,
which allows Stratix devices in all packages to interface with systems of
different supply voltages.
The Stratix VCCINTpins must always be connected to a 1.5-V power
supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and
3.3-V tolerant. The VCCIOpins can be connected to either a 1.5-V, 1.8-V,
2.5-V, or 3.3-V power supply, depending on the output requirements.
Altera Corporation
July 2005
2–129
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
