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EP1S80B1508C7ES 参数 Datasheet PDF下载

EP1S80B1508C7ES图片预览
型号: EP1S80B1508C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用:
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
f
For more information on I/O standards supported by Stratix devices, see  
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the  
Stratix Device Handbook, Volume 2.  
Stratix devices contain eight I/O banks in addition to the four enhanced  
PLL external clock out banks, as shown in Figure 2–70. The four I/O  
banks on the right and left of the device contain circuitry to support high-  
speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and  
HyperTransport inputs and outputs. These banks support all I/O  
standards listed in Table 2–31 except PCI I/O pins or PCI-X 1.0, GTL,  
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O  
banks support all single-ended I/O standards. Additionally, Stratix  
devices support four enhanced PLL external clock output banks,  
allowing clock output capabilities such as differential support for SSTL  
and HSTL. Table 2–32 shows I/O standard support for each I/O bank.  
2–124  
Stratix Device Handbook, Volume 1  
Altera Corporation  
July 2005  
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