Stratix Architecture
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–52 shows a diagram of the enhanced PLL.
Figure 2–52. Stratix Enhanced PLL
Programmable
Time Delay on
Each PLL Port
Post-Scale
Counters
VCO Phase Selection
Selectable at Each
PLL Output Port
From Adjacent PLL
/l0
/l1
Δt
Δt
Regional
Clocks
Clock
Switch-Over
Circuitry
Spread
Spectrum
Phase Frequency
Detector
INCLK0
INCLK1
4
8
/n
Δt
Charge
Pump
Loop
Filter
Global
Clocks
Δt
/g0
PFD
VCO
/g1
/g2
Δt
Δt
Δt
/m
(1)
I/O buffers
(2)
/g3
Δt
Δt
To I/O buffers or general
routing
Lock Detect
& Filter
FBIN
/e0
/e1
VCO Phase Selection
Affecting All Outputs
Δt
Δt
4
/e2
/e3
Δt
I/O Buffers (3)
Notes to Figure 2–52:
(1) External feedback is available in PLLs 5 and 6.
(2) This single-ended external output is available from the g0 counter for PLLs 11 and 12.
(3) These four counters and external outputs are available in PLLs 5 and 6.
(4) This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
Altera Corporation
July 2005
2–87
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
