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EP1S10F1508I7ES 参数 Datasheet PDF下载

EP1S10F1508I7ES图片预览
型号: EP1S10F1508I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用: 可编程逻辑
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
The DSP block consists of the following elements:  
Multiplier block  
Adder/output block  
Multiplier Block  
The DSP block multiplier block consists of the input registers, a  
multiplier, and pipeline register for pipelining multiply-accumulate and  
multiply-add/subtract functions as shown in Figure 2–32.  
Figure 2–32. Multiplier Sub-Block within Stratix DSP Block  
sign_a (1)  
sign_b (1)  
aclr[3..0]  
clock[3..0]  
ena[3..0]  
shiftin A  
shiftin B  
D
Q
Data A  
Result  
to Adder  
blocks  
ENA  
D
Q
ENA  
CLRN  
Optional  
CLRN  
Multiply-Accumulate  
and Multiply-Add  
Pipeline  
D
Q
Data B  
ENA  
CLRN  
shiftout B shiftout A  
Note to Figure 2–32:  
(1) These signals can be unregistered or registered once to match data path pipelines if required.  
Altera Corporation  
July 2005  
2–57  
Stratix Device Handbook, Volume 1  
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