Stratix Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix devices.
Table 2–1. Stratix Device Resources
M512 RAM
Columns/Blocks Columns/Blocks
M4K RAM
M-RAM
Blocks
DSP Block
Columns/Blocks Columns
LAB
Device
LAB Rows
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
4 / 94
6 / 194
6 / 224
7 / 295
8 / 384
10 / 574
11 / 767
2 / 60
2 / 82
1
2
2
4
4
6
9
2 / 6
40
52
30
41
46
57
61
73
91
2 / 10
2 / 10
2 / 12
2 / 14
2 / 18
2 / 22
3 / 138
3 / 171
3 / 183
4 / 292
4 / 364
62
67
77
90
101
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local
interconnect, LUT chain, and register chain connection lines. The local
interconnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s
register within an LAB. The Quartus® II Compiler places associated logic
within an LAB or adjacent LABs, allowing the use of local, LUT chain,
and register chain connections for performance and area efficiency.
Figure 2–2 shows the Stratix LAB.
Logic Array
Blocks
Altera Corporation
July 2005
2–3
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
