Stratix Architecture
and/or output enable registers. A programmable delay exists to increase
the tZX delay to the output pin, which is required for ZBT interfaces.
Table 2–24 shows the programmable delays for Stratix devices.
Table 2–24. Stratix Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Decrease input delay to internal cells
Decrease input delay to input register
Increase delay to output pin
Output enable register tCO delay
Output tZX delay
Increase delay to output enable pin
Increase tZX delay to output pin
Increase output clock enable delay
Increase input clock enable delay
Output clock enable delay
Input clock enable delay
Logic array to output register delay Decrease input delay to output register
Output enable clock enable delay Increase output enable clock enable delay
The IOE registers in Stratix devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power-up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally a
synchronous reset signal is available for the IOE registers.
Double-Data Rate I/O Pins
Stratix devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 2–65 shows an IOE configured for DDR input. Figure 2–66 shows
the DDR input timing diagram.
Altera Corporation
July 2005
2–111
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
