Stratix Device Family Data Sheet
Chapter
Date/Version
Changes Made
2
July 2003, v2.0
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Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK
connections.
Updated ranges for EPLL post-scale and pre-scale dividers on page
2-85.
Updated PLL Reconfiguration frequency from 25 to 22 MHz on page
2-87.
New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 2-96).
Updated max input frequency for CLK[1,3,8,10]from 462 to 500,
Table 2-24.
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Renamed impedance matching to series termination throughout.
Updated naming convention for DQS pins on page 2-112 to match pin
tables.
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Added DDR SDRAM Performance Specification on page 2-117.
Added external reference resistor values for terminator technology
(page 2-136).
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Added Terminator Technology Specification on pages 2-137 and 2-
138.
Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for
high speed differential channels at full speed.
Wire bond package performance specification for “high” speed
channels was increased to 624 Mbps from 462 Mbps throughout
chapter.
3
July 2005, v1.3
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Updated “Operating Modes” section.
Updated “Temperature Sensing Diode” section.
Updated “IEEE Std. 1149.1 (JTAG) Boundary-Scan Support” section.
Updated “Configuration” section.
January 2005, v1.2
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Updated limits for JTAG chain of devices.
September 2004, v1.1
Added new section, “Stratix Automated Single Event Upset (SEU)
Detection” on page 3–12.
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Updated description of “Custom-Built Circuitry” on page 3–13.
April 2003, v1.0
July 2005 v3.3
No new changes in Stratix Device Handbook v2.0.
4
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Updated Tables 4–6 and 4–30.
Updated Tables 4–103 through 4–108.
Updated Tables 4–114 through 4–124.
Updated Table 4–129.
Added Table 4–130.
Altera Corporation
Section I–3
ALTERA [ ALTERA CORPORATION ]
