Timing Model
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density. All of the timing parameters
in this section apply to both flip-chip and wire-bond packages.
Tables 4–103 and 4–104 show the input adder delays associated with
column and row I/O pins. If an I/O standard is selected other than 3.3-V
LVTTL or LVCMOS, add the selected delay to the external tINSU and
tINSUPLL I/O parameters shown in Tables 4–54 through 4–96.
Table 4–103. Stratix I/O Standard Column Pin Input Delay Adders
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
0
0
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
19
19
22
26
221
352
–45
–75
0
232
369
–48
–79
0
266
425
–55
–91
0
313
500
–64
–107
0
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
0
0
0
0
0
0
0
0
0
0
0
0
AGP 2×
0
0
0
0
CTT
120
–162
–162
–202
–202
78
126
–171
–171
–213
–213
81
144
–196
–196
–244
–244
94
170
–231
–231
–287
–287
110
110
–108
–108
–74
–74
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
78
81
94
–76
–76
–52
–52
–80
–80
–55
–55
–92
–92
–63
–63
4–66
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
