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EP1S40F1020C7 参数 Datasheet PDF下载

EP1S40F1020C7图片预览
型号: EP1S40F1020C7
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: LTE可编程逻辑
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3. Configuration & Testing  
S51003-1.3  
All Stratix® devices provide JTAG BST circuitry that complies with the  
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be  
performed either before or after, but not during configuration. Stratix  
devices can also use the JTAG port for configuration together with either  
the Quartus® II software or hardware using either Jam Files (.jam) or Jam  
Byte-Code Files (.jbc).  
IEEE Std. 1149.1  
(JTAG)  
Boundary-Scan  
Support  
Stratix devices support IOE I/O standard setting reconfiguration through  
the JTAG BST chain. The JTAG chain can update the I/O standard for all  
input and output pins any time before or during user mode through the  
CONFIG_IOinstruction. You can use this ability for JTAG testing before  
configuration when some of the Stratix pins drive or receive from other  
devices on the board using voltage-referenced standards. Since the Stratix  
device may not be configured before JTAG testing, the I/O pins may not  
be configured for appropriate electrical standards for chip-to-chip  
communication. Programming those I/O standards via JTAG allows you  
to fully test the I/O connection to other devices.  
The enhanced PLL reconfiguration bits are part of the JTAG chain before  
configuration and after power-up. After device configuration, the PLL  
reconfiguration bits are not part of the JTAG chain.  
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The  
TDOpin voltage is determined by the VCCIO of the bank where it resides.  
The VCCSELpin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or  
3.3-V compatible.  
Stratix devices also use the JTAG port to monitor the logic operation of the  
device with the SignalTap® II embedded logic analyzer. Stratix devices  
support the JTAG instructions shown in Table 3–1.  
The Quartus II software has an Auto Usercode feature where you can  
choose to use the checksum value of a programming file as the JTAG user  
code. If selected, the checksum is automatically loaded to the USERCODE  
register. In the Settings dialog box in the Assignments menu, click Device  
& Pin Options, then General, and then turn on the Auto Usercode  
option.  
Altera Corporation  
July 2005  
3–1